Split package - package body with deferred type definitions?

[David Rogoff]

Hi all.

Getting back into some VHDL verification after many years of SystemVerilog. Question about packages and deferred definitions.

Test environment has main test split into separate entity and architecture files so that 1) entity can be compiled once with RTL and only architecture file needs to be recompiled when changes, and 2) multiple architecture files can be configured to the single entity.

This works great. I'm now trying to extend this concept with a package to be used by this test file. Again, I'm setting up the package and package body in separate files so the test entity can "use" the package file and multiple package body files (each corresponding to the test architecture files) would have the local definitions of things.

This is fine for constants and procedures since I can put the prototype in the package file and then the deferred constant assignment and procedure bodies in the package body files. So far, so good.

However, it all dies for the type definitions. Each package body needs to define its own version of the types. It doesn't look like there's such a thing as deferred type declarations.

Am I missing something? Another way to implement this concept? I can brute-force a Verilog/C-like `define by using the compile script to concatenate the package body file (minus the package body/end package body lines) and the architecture file into one (inserting the "package" after the "architecture xx of yy is" line) and compiling that. Ugly, but it should work.

Help!

Thanks,

David

[Jim Lewis]

Hi David,
Have you considered using generics on packages? This is a VHDL-2008 feature.

With VHDL-2008, generics can be put on packages, and generics can be constants (the pre-2008 generic), types, subprograms, and generic packages. The following shows a simple sketch of a package with type and subprogram generics:

package ScoreBoardPkg is
generic (
type BaseType ;
function check(A, E : BaseType) return boolean
) ;
-- remaining part of package goes here
end ScoreBoardPkg ;

To use the generic package you must create a package instance. This is done as follows:
library IEEE ;
use ieee.std_logic_1164.all ;
package ScoreBoardPkg_slv8 is new work.ScoreBoardPkg
generic map (
BaseType => std_logic_vector(7 downto 0),
check => std_match
) ;

If you are looking for features such as randomization and functional coverage, be sure to check out the Open Source VHDL Verification Methodology page at http://www.osvvm.org

If you are looking for training on OSVVM and Advanced VHDL Verification techniques, see http://synthworks.com/vhdl_testbench_verification.htm

Best Regards,
Jim

[David Rogoff]

Post by Jim Lewis
Hi David,
Have you considered using generics on packages? This is a VHDL-2008 feature.
With VHDL-2008, generics can be put on packages, and generics can be constants (the pre-2008 generic), types, subprograms, and generic packages.
Best Regards,
Jim

Thanks Jim. I briefly thought about generics but didn't look into the details. I'll have to take some time with that. I think it could work but might be really messy given the number and size of some type enums I need to deal with.

David